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CS4192 Single Air-Core Gauge Driver
The CS4192 is a monolithic BiCMOS integrated circuit used to translate a digital 10-bit word from a microprocessor/microcontroller to complementary DC outputs. The DC outputs drive an air-core meter commonly used in vehicle instrument panels. The 10 bits of data are used to linearly control the quadrature coils of the meter directly with a 0.35 resolution and 1.2 accuracy over the full 360 range of the gauge. The interface from the microcontroller is by a Serial Peripheral Interface (SPI) compatible serial connection using up to a 2.0 MHz shift clock rate. The digital code, which is directly proportional to the desired gauge pointer deflection, is shifted into a DAC and multiplexer. These two blocks provide a tangential conversion function to change the digital data into the appropriate DC coil voltage for the angle demanded. The tangential algorithm creates approximately 40% more torque in the meter movement than does a sin-cos algorithm at 45, 135, 225, and 315 angles. This increased torque reduces the error due to pointer droop at these critical angles. Each output buffer is capable of supplying up to 70 mA per coil and the buffers are controlled by a common OE enable pin. The output buffers are turned off when OE is brought low, while the logic portion of the chip remains powered and continues to operate normally. OE must be high before the falling edge of CS to enable the output buffers. The status pin (ST) reflects the state of the outputs and is low whenever the outputs are disabled. The Serial Gauge Driver is self-protected against fault conditions. Each driver is protected for 125 mA (typ.) overcurrent while a global thermal protection circuit limits junction temperature to 170C (typ.). The output drivers are disabled anytime the IC protection circuitry detects an overcurrent or overtemperature fault. The drivers remain disabled until a falling edge is presented on CS. If the fault is still present, the output drivers automatically disable themselves again. Features * Serial Input Bus * 2.0 MHz Operating Frequency * Tangential Drive Algorithm * 70 mA Drive Circuits * 0.5 Accuracy (Typ.) * Power-On-Reset * Protection Features - Output Short Circuit - Overtemperature * Internally Fused Leads in SO-16L Package
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16 1 SO-16L DWF SUFFIX CASE 751G
PIN CONNECTION AND MARKING DIAGRAM
1 SIN- SIN+ VBB GND GND SI VCC OE 16 COS+ COS- SO GND GND ST CS SCLK
AWLYYWW
CS4192
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device CS4192XDWF16 CS4192XDWFR16 Package SO-16L SO-16L Shipping 46 Units/Rail 1000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2001
1
December, 2001 - Rev. 6
Publication Order Number: CS4192/D
CS4192
VCC VBB
POR
LOGIC
SI SCLK CS
Serial to Parallel Shift Register
VTOP D0-D6 7 Bit DAC VVAR VBAT MUX
SO D7-D9 POR R FAULT Latch S Q Overcurrent
ST
ENA
OE
GND
Figure 1. Block Diagram
MAXIMUM RATINGS*
Rating Supply Voltage Digital Inputs Steady State Output Current Forced Injection Current (Inputs and Supply) Operating Junction Temperature, (TJ) Storage Temperature Range Lead Temperature Soldering ESD Susceptibility (Human Body Model) Package Thermal Resistance, SO-16L Junction-to-Case, RJC Junction-to-Ambient, RJA 1. 60 seconds max above 183. *The maximum package power dissipation must be observed. Reflow (SMD styles only) Note 1 VBB VCC Value -1.0 to 16.5 -1.0 to 6.0 -1.0 to 6.0 100 10 150 -65 to 150 230 peak 2.0 18 75 Unit V V mA mA C C C kV C/W C/W
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CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC
Output Amplifiers Overtemp
SIN+ SIN- COS+ COS-
CS4192
ELECTRICAL CHARACTERISTICS (-40C TJ 105C; 7.5 V VBB 14 V, 4.5 V VCC 5.5 V;
unless otherwise specified. Note 2.) Characteristic Supply Voltages and Currents VBB Quiescent Current Output disabled (OE = 0 V) [RCOS, RSIN = RL(MIN)] @ 45 (code = X'080) VBB = 14 V OE, CS, DI = high, VBB = 0 V, SCLK = 2.0 MHz - - - 1.0 - - 5.0 175 1.15 mA mA mA Test Conditions Min Typ Max Unit
VCC Quiescent Current Digital Inputs and Outputs Output High Voltage Output Low Voltage Output Off Leakage Input High Voltage Input Low Voltage Input High Current Input Low Current Analog Outputs Output Function Accuracy Output Shutdown Current, Source Output Shutdown Current, Sink Output Shutdown Current, Source Output Shutdown Current, Sink Thermal Shutdown Thermal Shutdown Hysteresis Coil Drive Output Voltage Minimum Load Resistance
SO, IOH = 0.8 mA SO, IOL = 0.8 mA ST, IOL = 2.5 mA ST, VCC = 5.0 V CS, SCLK, SI, OE CS, SCLK, SI, OE CS, SCLK, SI, OE; VIN = 0.7 x VCC CS, SCLK, SI, OE; VIN = 0.3 x VCC
VCC - 0.8 - - - 0.7 x VCC - - -
- - - - - - - -
- 0.4 0.8 25 - 0.3 x VCC 1.0 1.0
V V V A V V A A
- VBB = 14 V VBB = 14 V VBB = 7.5 V VBB = 7.5 V - - - TA = 105C TA = 25C TA = -40C - - - 0.75 V to VCC - 1.2 V; CL = 90 pF 0.75 V to VCC - 1.2 V; CL = 90 pF CL = 90 pF - - Note 3. -
-1.2 70 70 43 43 - - - - - - - 175 175 - - - 75 75 0 75
0.5 125 125 125 125 170 20 0.748 x VBB 229 171 150 - - - - - - - - - -
+1.2 250 250 250 250 - - - - - - 2.0 - - 150 150 150 - - - -
deg mA m m m C C V MHz ns ns ns ns ns ns ns ns ns
Shift Clock Frequency SCLK High Time SCLK Low Time SO Rise Time SO Fall Time SO Delay Time SI Setup Time SI Hold Time CS Setup Time CS Hold Time
2. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested in production. 3. OE must be high at falling edge of CS. This condition ensures valid output for any given input.
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CS4192
PIN FUNCTION DESCRIPTION
PACKAGE PIN # 16 Lead SO Wide 1 2 3 4, 5, 12, 13 6 7 SIN- SIN+ VBB GND SI VCC Negative output for SINE coil. Positive output SINE coil. Analog supply. Nominally 13.5 V. Ground. Serial data input. Data present at the rising edge of the clock signal is shifted into the internal shift register. 5.0 V logic supply. The internal registers and latches are reset by a POR generated by the rising edge of the voltage on this pin. Controls the state of the output buffers. A logic low on this pin turns them off. Serial clock for shifting in/out of data. Rising edge shifts data on SI into the shift register and the falling edge changes the data on SO. When high allows data at SI to be shifted into part with the rising edges of SCLK. The falling edge transfers the shift register contents into the DAC and multiplexer to update the output buffers. The falling edge also reenables the output drivers if they have been disabled by a fault. STATUS reflects the state of the outputs and is low anytime the outputs are disabled, either by OE or the internal protection circuitry. Requires external pull-up resistor. Serial data output. Existing 10-bit data is shifted out when new data is shifted in. Allows cascading of multiple devices on common serial port. Negative output for COSINE coil. Positive output for COSINE coil. PIN SYMBOL FUNCTION
8 9
OE SCLK
10
CS
11
ST
14
SO
15 16
COS- COS+
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CS4192
APPLICATIONS INFORMATION
THEORY OF OPERATION Quadrant II q + 180-Tan-1 VSIN) * VSIN* VCOS) * VCOS*
The SACD is for interfacing between a microcontroller or microprocessor and air-core meter movements commonly used in automotive vehicles for speedometers and tachometers. These movements are built using two coils placed at a 90 orientation to each other. A magnetized disc floats in the middle of the coils and responds to the magnetic field generated by each coil. The disc has a shaft attached to it that protrudes out of the assembly. A pointer indicator is attached to this shaft and in conjunction with a separate printed scale displays the vehicle's speed or the engine's speed. The disc (and pointer) respond to the vector sum of the voltages applied to the coils. Ideally, this relationship follows a sine/cosine equation. Since this is a transcendental and non-linear function, devices of this type use an approximation for this relationship. The SACD uses a tangential algorithm as shown in Figure 2. Only one output varies in any 45 degree range.
Degrees of Rotation 0 Max(128) 45 90 135 180 225 270 315 360
For q + 90.176to 134.824 : VSIN + 0.748 VBB 0.748 VBB VCOS + *Tan (q * 90) For q + 135.176to 179.824 : VSIN + Tan(180 * q) VCOS + *0.748 Quadrant III q + 180 ) Tan-1 VSIN) * VSIN* VCOS) * VCOS* VBB 0.748 VBB
For q + 180.176to 224.824 : VSIN + *Tan (q * 180) VCOS + *0.748 VBB 0.748 VBB
SIN+ Output Min(0)
Max(128)
For q + 225.176to 269.824 : VSIN + *0.748 VBB 0.748 VBB VCOS + *Tan (270 * q) Quadrant IV VSIN) * VSIN* q + 360 * Tan-1 VCOS) * VCOS* For q + 270.176to 314.824 : VSIN + *0.748 VBB 0.748 VBB VCOS + Tan(q * 270)
001 010 011 100 101 110 111 000
SIN- Output Min(0)
Max(128)
COS+ Output
Min(0) Max(128)
COS- Output Min(0)
000
MUX bits (D9-D7)
For q + 315.176 * 359.824 : VSIN + *Tan (360 * q) VCOS + 0.748 VBB 0.748 VBB
Figure 2. SIN, COS Outputs Quadrant I VSIN) * VSIN* q + Tan-1 VCOS) * VCOS* For q + 0.176to 44.824 : VSIN + Tanq VCOS + 0.748 0.748 VBB VBB
For q + 45.176to 89.824 : VSIN + 0.748 VBB VCOS + Tan(90 * q) 0.748 VBB
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CS4192
VCOS+ 360/0 0.748 VBB
IV I
270 VSIN-
0.748 VBB
III
0.748 VBB
II
90 VSIN+
The 10 bits are shifted into the device's shift register MSB first using an SPI compatible scheme. This method is shown in Figure 5. The CS must be high and remain high for SCLK to be enabled. Data on SI is shifted in on the rising edge of the synchronous clock signal. Data in the shift register changes at SO on the falling edge of SCLK. This arrangement allows the cascading of devices. SO is always enabled. Data shifts through without affecting the outputs until CS is brought low. At this time the internal DAC is updated and the outputs change accordingly.
CS
0.748 VBB 180 VCOS-
SCLK
SI(Setup)
CSSetup
CSHold
Figure 3. Gauge Response
SI
SI(Hold)
To drive the gauge's pointer to a particular angle, the microcontroller sends a 10-bit digital word into the serial port. These 10 bits are divided as shown in Figure 4.
MSB Gauge (360) D9 D8 D7 D6 D5 D4 D3 D2 D1
D9-D7 select which octant
SO
SI(tpd)
SO(Rise, Fall) 10% - 90%
LSB D0
Divides a 45 octant into 128 equal parts to achieve a 0.35 resolution Code 0-12710
Figure 5. Serial Data Timing Diagram
Figure 4. Definition of Serial Word
Figure 6 shows the power-up sequence for the CS4192. Note the IC requires a pulse on the Chip Select (CS) pin to clear the Status Fault (ST) after power up. OE must be high before the falling edge of CS to enable the output buffers.
However, from a software programmers viewpoint, a 360 circle is divided into 1024 equal parts of 0.35 each. Table 1 shows the data associated with the 45 divisions of the 360 driver.
Table1. Nominal Output (VBB = 14 V)
Input Code (Decimal) 0 128 256 384 512 640 768 896 1023 Ideal Degrees 0 45 90 135 180 225 270 315 359.65 Nominal Degrees 0.176 45.176 90.176 135.176 180.176 225.176 270.176 315.176 359.826 VSIN (V) 0.032 10.476 10.476 10.412 -0.032 -10.476 -10.476 -10.476 -0.032 VCOS (V) 10.476 10.412 -0.032 -10.476 -10.476 -10.412 0.032 10.476 10.476
VCC CS SI 10 Bits
Registers set to zero
10 Bits
ST
OUTPUTS ENABLED
Registers set to zero
OE
OUTPUTS ENABLED
Figure 6. Power Up Sequence
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CS4192
VBATT VREG CS8156 5.0 V 12 V ENABLE 360 Gauge
CS4192 10 k SIN- SIN+ ST CS SI SCLK OE COS+ COS- VBB VCC
Microcontroller
SO
Next Driver
Figure 7. Application Diagram
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CS4192
PACKAGE DIMENSIONS
SO-16L DWF SUFFIX CASE 751G-03 ISSUE B
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1 16X
8
B TA
S
B B
S
0.25
M
A
h X 45_
SEATING PLANE
M
8X
0.25
E
A1
14X
e
T
C
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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L
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CS4192/D

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